The effort to redefine how AI systems communicate has taken another step forward, as the UALink Consortium released version 2.0 of its interconnect specification, well before hardware based on its first iteration has reached the market.
The consortium, backed by companies including AMD, Cisco, and Hewlett Packard Enterprise, is positioning UALink as an open alternative to proprietary technologies like NVIDIA’s NVLink. As AI workloads expand rapidly, infrastructure providers are under pressure to improve how accelerators such as GPUs exchange data at scale, and UALink aims to create a standard for this process.
Release 2.0 includes introduction of in-network compute, a capability designed to merge communication and computation across connected accelerators. Rather than simply moving data between chips, the network itself can now participate in processing tasks. The consortium claims the result is reduced latency and more efficient use of bandwidth, two constraints that have become more problematic as AI models grow in complexity.
The updated specification also focuses on scaling efficiency for distributed training and inference, a key requirement for hyperscale AI deployments. By reducing the overhead associated with coordinating workloads across hundreds or thousands of processors, UALink aims to improve performance in multi-node environments.
Additional Specs
Beyond the headline features, the consortium introduced several complementary specifications. A revised 200G data link and physical layer standard separates transport and protocol development, allowing faster iteration as networking speeds evolve toward 400G and beyond. A new manageability specification defines centralized control mechanisms using established interfaces such as gNMI and Redfish, while a chiplet-focused standard outlines how UALink can be integrated into modular system-on-chip designs.
This modular approach in particular is notable. By enabling interoperability across vendors and hardware types, UALink’s architects are attempting to replicate the ecosystem dynamics that made Ethernet dominant, an open framework where multiple suppliers compete while adhering to shared standards.
Competing with NVIDIA
For all its promise, the effort remains largely theoretical. Despite the release of version 1.0 in 2025, silicon implementing the specs is not expected to appear in meaningful volume until late 2026, with commercial products likely arriving in 2027.
This ambitious timeline is not unusual for standards bodies, but it does highlight the scale of NVIDIA’s current advantage. The company’s NVLink and NVSwitch technologies are already widely deployed in AI data centers, delivering tightly integrated performance that competitors are still working to match.
The consortium acknowledges that parity will not come immediately. Leadership has indicated that only future iterations, potentially version 3.0, will approach the performance and maturity of NVIDIA’s offerings. Still, the motivation remains strong. Many cloud providers and emerging neocloud vendors are eagerly seeking alternatives that avoid dependence on NVIDIA, particularly as demand for AI infrastructure drives up costs.
Nvidia, for its part, has expanded access to its interconnect through initiatives such as NVLink Fusion, allowing partners including Arm and Qualcomm to integrate custom processors with its GPUs. It has also participated in other open networking efforts, signaling a pragmatic approach to a diversifying ecosystem.
The emergence of UALink 2.0, then, is less a direct challenge than a long-term play. It reflects a growing consensus that AI infrastructure will require more flexible, multi-vendor connectivity models. But the exact shape of that connectivity model remains a work in progress.
